With its new Maverick-2 accelerator, NextSilicon is betting on a long-pursued approach to accelerating HPC and data center workloads, known as dataflow computing.
Every so often, a semiconductor startup emerges claiming to have cracked a problem the industry’s biggest players have wrestled with for decades. Most fade quietly, but occasionally, one arrives that turns heads as a potential disruptor of the industry.
NextSilicon, an Israel-based compute architecture firm founded by CEO Elad Raz back in 2017, appears to be one of those rare cases. With its new Maverick-2 accelerator, built on what the company calls an Intelligent Compute Architecture,a long-pursued but rarely realized approach to accelerating HPC and data center workloads, known as dataflow computing. A dataflow architecture is designed such that the data itself, not instruction sequences, drives computation. The company believes it’s finally solved the twin barriers that kept dataflow architectures confined to research labs: programmability and practicality.Modern computing remains largely defined by a concept called the Von Neumann model, a design that has served faithfully for over 80 years. CPUs and GPUs alike spend enormous amounts of silicon area shuffling instructions, managing branch predictions, and juggling cache coherency — doing an inordinate amount work over and above the actual math that a workload requires and developers care most about. CPUs still dominate for their flexibility, but they’re relatively inefficient. GPUs deliver significant parallel processing horsepower but require specialized programming and tight ecosystem dependence. ASICs typically offer extraordinary efficiency yet lock customers into single-purpose hardware at a huge cost impact. NextSilicon’s proposition is simple but perhaps audacious: what if there was a fourth way — a compute engine as efficient as an ASIC, as parallel as a GPU, and as flexible as a CPU? At least that’s the goal of the company and it’s claiming a significant milestone has been achieved in that effort with its Maverick-2 accelerator.NextSilicon Dual-Die Maverick-2 OAM Accelerator With 192GB Of HBM3E MemoryAt the heart of NextSilicon’s new Maverick-2 accelerator is a dataflow execution fabric. Instead of relying on a program counter to step through instructions, the processor’s arithmetic logic grid, which is proprietary custom logic, activates whenever input data becomes available. Imagine an automated factory where every station starts work the moment its materials arrive, rather than waiting for a central manager to issue commands. At a very basic level, this is the model of dataflow computing. This model allows the hardware to devote far more of its silicon area to compute resources rather than control functions — a reversal of traditional CPU designs where the vast majority of transistors must be dedicated to instruction handling. In theory, a dataflow processor architecture should translate to significantly higher utilization of silicon resources for compute and much better power efficiency. NextSilicon claims its Maverick-2 can achieve up to 10X the performance of top GPUs while consuming up to 60 percent less power, all while running unmodified C++, Python, Fortran, or other framework code. Developers and software engineers are accustomed to months-long porting efforts for each new platform, but this is not the case with Next Silicon’s solution. The company also underscores that code based on Nvidia’s CUDA programming language for GPU AI accelerators can also run on Maverick-2 efficiently, again completely unmodified.Typically, 90+ percent of a workload is processed by only a few specific calculations and this is another area where NextSilicon’s technology reportedly shines. NextSilicon claims that Maverick-2’s software layer profiles existing code in real time, identifies computational hot spots, and dynamically reconfigures compute resources — effectively turning a static chip into a self-optimizing engine. The optimizer constantly monitors what the application is doing, which parts of the code run most often and what data patterns emerge. Using that live telemetry, it automatically builds and compiles specialized hardware configurations known as “Mill Cores” and saves them as ready-to-use images in the chip’s memory. These optimizations happen seamlessly in the background, without slowing down the workload. When a performance-critical part of the application appears, the hardware instantly reconfigures itself in nanoseconds using those pre-built images. Unlike traditional systems that make assumptions at compile time, Maverick-2 optimizes itself based on runtime behavior, reshaping itself for each workload. One moment it can be tuned for massive parallelism, the next for deep pipelining. As a result, you get near-ASIC efficiency with the flexibility to adapt dynamically as an application or system use case evolves. This kind of on-the-fly adaptability could be game-changing for workloads ranging from HPC simulations to data analytics, AI training and AI inference. As an aside, NextSilicon details that Maverick-2 also offers either single or dual 100 Gigabit Ethernet connectivity for scalability.NextSilicon Maverick-2 Performance Claims And Memory ConfigurationUnlike most early-stage chip architectures, Maverick-2 isn’t just slideware. The chip is already deployed in systems such asAccording to internal benchmarks shared by Next Silicon:, Maverick-2 reportedly runs 22× faster than CPUs and nearly 6× faster than GPUs.benchmark, it delivers performance on par with top GPUs while using about half the power. In PageRank, a graph analytics test for web page authority ranking, it completed large graphs that leading GPUs failed to finish. These figures were obtained in a company-controlled environment, which of course calls for independent, 3party validation. Sandia’s commitment to validating the Maverick-2 platform, however, suggests that NextSilicon’s solution is worthy of significant investment.NextSiliconCPU core that was born from an integral part of the Maverick-2 architecture. Maverick-2 has a RISC-V control processor that handles the serial logic and orchestration to keep the chip’s massive dataflow grid running efficiently. Essentially, it serves as the air-traffic controllers of the system, coordinating the movement of data so its parallel compute fabric stays fully utilized. NextSilicon developed it for implementation in its Maverick-2 accelerator and it was so good they decided to market it separately as well. Called Arbel, and scaled-up a bit to stand on its own for even host CPU applications, Next Silicon claims its RISC-V core tests chip is potentially the highest-performing RISC-V CPU core design on the market. The company points to features like a 10-wide issue pipeline, deep reorder buffer, and integrated vector units built on TSMC’s 5 nm node If true, this would mean Maverick-2’s control plane isn’t merely keeping pace with its dataflow side, it’s also pushing the boundaries of RISC-V performance. Still, that claim awaits independent validation. For now, the key takeaway is that NextSilicon is implementing tight integration of high-speed scalar control with adaptive dataflow compute for utilization efficiency traditional accelerators lack.NextSilicon If Maverick-2 delivers its claimed performance-per-watt advantage, it could be one of the most important compute architecture breakthroughs of the decade. The energy savings alone would be huge forHowever, architecture is only half the story. The semiconductor market rewards ecosystem maturity, not just raw performance. Nvidia’s dominance and AMD’s emergence in AI aren’t just about silicon, they’re about complete platforms with programming libraries like CUDA, developer familiarity, full rack-scale solutions and years of optimization. NextSilicon says Maverick-2 runs completely unmodified code, but its long-term success will hinge on real integration into existing HPC and AI frameworks. Profilers, debugging tools, and runtime schedulers will need to support the architecture seamlessly. That’s a non-trivial lift for a smaller company taking on giants with software ecosystems measured in millions of developers. There’s also the question of manufacturing scale and supply chain. Maverick-2 is fabricated on one of TSMC’s advanced 5nm nodes, putting NextSilicon in line with the same foundry capacity crunch that affects every major semiconductor firm. How the company balances volume, cost, and delivery will matter as much as it performance metrics.That said, it’s clear to me that if NextSilicon’s technology holds up under independent validation, it could carve out a niche in HPC, simulation, and AI-driven scientific research, where customers value throughput and efficiency above all. The company’s claim of “drop-in programmability”—if proven—might then also open doors in hyperscaler data center acceleration and big data analytics. Longer term, Maverick-2’s success could push competitors to revisit traditional chip architecture assumptions. Nvidia is already pursuing tightly coupled CPU-GPU designs with its Grace-Blackwell architecture, for example. If Maverick-2 demonstrates that dataflow can coexist and run efficiently with standard code, it could force others to rethink how they balance parallelism and programmability.may represent one of the most credible attempts yet to make dataflow computing commercially viable. By fusing adaptive, software-defined hardware with embedded RISC-V control logic, it sidesteps the historical trade-offs between performance, flexibility, and cost that have constrained compute architectures for decades. But real disruption in high performance processors doesn’t happen in benchmarks; it happens in ecosystems. The company’s next challenge isn’t proving its chip works, it’s proving developers and customers can adopt it easily and profitably. If it can clear that bar, NextSilicon won’t just have built a faster more efficient accelerator, it will have rekindled the industry’s approach to far more efficient computing in the AI, HPC and exascale era.
AI Supercomputing Silicon Startups Dataflow Processor Nextsilicon Nextsilicon Maverick-2 Maverick-2
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