The company continues to express confidence in its roadmap and methodical, modular approach as it works to achieve large-scale fault-tolerant quantum computing by 2029.
IBM’s 300mm quantum processor wafer features multiple chips arranged in a grid pattern. The shift to 300mm wafer fabrication has doubled IBM’s development speed and enabled substantial increases in chip complexity.
At its second annual Quantum Developer Conference held recently in Atlanta, IBM presented updates on its roadmap initiatives for an audience of quantum developers, researchers and community leaders from around the world. New quantum processors, research tools and investigation methods hold promise for helping IBM achieve the breakthrough of quantum advantage — when a quantum solution is verified to be better than competing solutions that employ only classical computing., IBM believes that it is on track to achieve utility-scale fault-tolerant quantum computing by 2029. Whenever that milestone is achieved — by IBM or anyone else — it will be the result of 100-plus years of quantum research.IBM Nighthawk: Hunting For Near-Term Quantum Advantage Nighthawk is IBM’s next scheduled quantum processor on the roadmap. IBM calls Nighthawk its most advanced quantum processor to date. It has 120 qubits and is designed to facilitate high-performance quantum software with the goal of delivering quantum utility and quantum advantage at scale. According to IBM, Nighthawk will have faster execution speeds and, most importantly, the ability to run circuits that are 30% more complex on average thanks to improvements enabled by higher connectivity. IBM Quantum Nighthawk features 120 qubits in a square lattice with 218 couplers, enabling circuits that are 30% more complex than on its predecessor, Heron.Nighthawk is also IBM’s first chip with a square qubit topology. That shape increases the number of couplers from 176 to 218. You can think of increasing couplers as providing more ways for qubits to talk to each other. The new topology offers greater nearest-neighbor connectivity than Heron’s heavy-hex design. Square topology also allows Nighthawk to run circuits using fewer SWAP gates, which accounts for the increase in circuit complexity. By removing unnecessary SWAP gates, the design enables users and developers to take advantage of the freed-up space to add computational gates that carry out calculations while staying within the chip’s noise limits. Lastly, Nighthawk is designed to scale for both modularity and performance. IBM’s long-term modularity plan is to create larger systems by connecting multiple Nighthawk chips together.While the Nighthawk is designed to handle today’s problems, the Loon processor is a blueprint for a massive fault-tolerant machine. It is a proof-of-concept to test ideas for a quantum supercomputer. In the Loon processor, IBM’s c-coupler architecture uses additional routing layers to enable long-range connections between distant qubits on a chip.With Loon, IBM plans to implement qLDPC codes needed for fault-tolerant computing. You can read more aboutin the Forbes article I wrote in June. Loon’s design includes six-way qubit connections, increased layers of routing on the chip’s surface, physically longer couplers and a fast way to quickly reset qubits to ground state. IBM was able to test all of Loon’s features for the first time by using its new electronic design automation system. EDA is used to test and analyze complex chip architectures. IBM expects Loon to be fabricated and assembled by the end of 2025, with testing starting in early 2026; after that, it will be used to implement and scale components for practical, high-efficiency quantum error correction.Quantum error correction has a long history, going back to its origin as a theoretical possibility in 1995. It has since evolved into the current engineering reality of IBM’s FPGA decoder. This solution represents an important breakthrough because it demonstrates ultra-low latency and validates a path for scalable fault-tolerant computing. Because of the importance IBM assigned to it, this advanced decoding project for QEC was completed a year earlier than originally scheduled. For context, the quantum error correction syndrome cycle time is 1 microsecond. This is the result of the very fast gates of superconducting qubits relative to other quantum computing modalities. Because quantum states degrade rapidly, it is not enough to simply fix them; they must be found and fixed faster than new errors can arise and overwhelm the system. In practical terms, this means that QEC requires real-time decoding so that syndrome measurements can be decoded before the quantum circuit is allowed to run more than one or two operations. An overview of the Relay-BP FPGA decoder architecture — Source: T. Maurer, M. Bühler, M. Kröner, F. Haverkamp, D. Vandeth and B. R. Johnson, “Real-time decoding of the gross code memory with FPGAs,” IBM Quantum, October 24, 2025.IBM created a unique — and potentially major — error correction solution by implementing a special algorithm called Relay-BP on an off-the-shelf AMD FPGA. Its purpose is to translate syndrome data into error information used by qLDPC codes. The FPGA works well for error correction because it can complete decoding tasks in less than 480 nanoseconds — well under the 1-microsecond error correction cycle time. Given this, one would expect it to keep up with the syndrome cycle in real time. It is also significant that IBM uses standard, commercially available FPGAs to achieve its decoding speed, which is much faster than minimum requirements. IBM’s FPGA approach outperforms GPU-based solutions by an order of magnitude. Even though GPUs are favored by some groups, the GPU’s initialization time alone exceeds the FPGA’s entire decoding time. FPGAs can deliver sub-microsecond decoding with deterministic, predictable performance and with no startup delays. The FPGA solution has another advantage over GPUs: it can be embedded directly into quantum systems to eliminate data-transfer overhead. Summing it up, IBM has proven that quantum error correction can be implemented with existing, affordable technology capable of scaling along with quantum processor development. In this instance, clever engineering coupled with appropriate off-the-shelf hardware can meet quantum computing’s most challenging real-time requirements.Earlier this year, IBM published a framework to help researchers determine how and when quantum advantage has officially been achieved. Solid evidence is required to prove that a solution demonstrates quantum advantage. Proof can be presented in terms of computing power, efficiency, cost-effectiveness, accuracy or some combination of these. So far, the community has yet to find a solution that has a true quantum advantage. In general, achieving quantum advantage is largely restricted by hardware characteristics and by the number, type, depth and fidelity of qubits. In an attempt to find existing examples of quantum advantage, IBM initiated an investigation of existing algorithms and circuits that appear to be faster or more efficient than their classical counterparts. IBM has also joined forces with the Flatiron Institute, BlueQubit and Algorithmiq to create an open, community-led organization to track investigation of potential quantum-advantage activities. The newly formed organization is currently supporting three quantum advantage experiments across observable estimation, variational problems and problems with efficient classical verification.Shift from measuringEstablish competitive quantum leaderboardsMeasure time-to-solution for selected systems and benchmarks IBM expects that quantum advantage will be achieved and verified in 2026. Improved quantum hardware should demonstrate verifiable speed-ups over classical computing. New software tools are expected to enable algorithm development across wider integrated quantum-classical resources. IBM also plans to release advanced computational Qiskit libraries to support advanced subjects such as machine learning and optimization. Scientists will have access to these and other advanced resources to help solve fundamental physics and chemistry challenges in areas such as differential equations and Hamiltonian simulations. IBM seems confident that as it continues to deliver projects on its roadmap, and with assistance from the quantum community, the company will bring fault-tolerant quantum-centric supercomputing into reality on time.IBM’s roadmap lays out a methodical and practical approach to achieving fault-tolerant quantum computing. The Nighthawk processor aims to produce near-term utility improvements, while Loon’s purpose is to validate the architectural components needed for qLDPC. Modular design means that once individual modules are proven to be reliable, scaling them up into larger systems should be a simple matter of connecting additional modules. The company’s timeline for achieving quantum advantage in 2026 coordinates advancement across qubit coherence, gate fidelities, error correction codes, control systems and decoder algorithms. The validation and integration of each of these technologies is essential for reliable quantum fault tolerance. Achieving quantum advantage next year would represent a significant milestone in the history of computation. If it further enables utility-scale FTQC by the end of this decade, that will have a significant impact on the world. Moor Insights & Strategy provides or has provided paid services to technology companies, like all tech industry research and analyst firms. These services include research, analysis, advising, consulting, benchmarking, acquisition matchmaking and video and speaking sponsorships. Of the companies mentioned in this article, Moor Insights & Strategy currently has a paid business relationship with AMD and IBM.
Quantum Advantage FPGA FTQC Error Correction QEC
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