Gone are the days of the big stick – using the latest, fastest, and biggest processor to do everything. Customization at the silicon, packaging, and even the instruction set level is now required to ensure performance efficiency
One area of customization that has become most evident in demonstrating this is in the use of specialized functional hardware blocks for critical chip functions such as I/O, power management, security, on-chip networking, and even the workload processing itself. Because of this specialization, most processors are now bundled with additional hardware functions, collectively referred to as a System-on-Chip .
Often lumped in with the Arm architecture as “processor cores,” configurable processor cores offer customization options not available with the Arm architecture. Arm processor IP cores provide the same instruction set to everyone, which confers software compatibility between SoC designs but does not provide the ability to add custom instructions that increase the execution and performance efficiency for specific functions or algorithms.
Synopsys ARC, RISC-V and Cadence Tensilica processors were designed to support custom instructions from the ground up, which means it’s practical to tailor these cores for SoCs designed for even embedded/IoT applications that may be performing very limited tasks. Optimizing even those tasks can improve performance and/or lower power consumption. Customization requires software tools for mapping the code to the custom instructions.
The ARC architecture is a family of IP processors, many optimized for specific types of applications, such as low-power, safety-critical, high-security, high-throughput, high-performance applications, and even AI inference processing. All of these applications benefit from customized instructions.
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