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Cadence has updated its platforms that supports chip design teams, offering more than 2X more capacity and 1.5X faster performance than the previous generation and can support chips up to 48 billion gates.
Designing and testing chips is constantly becoming more difficult, requiring software and emulation hardware that can keep up with the growth in transistors. And of course the emergence of chiplets adds a new dimension. As the challenges grow, so must the hardware used to emulate and debug the chip and prepare the software that will run on the semiconductor once it is back from the fab.
Cadence offers emulation and prototyping hardware to support this iterative development process. The new Palladium Z3 system accelerates hardware verification, and through functional and interface congruency, models can be quickly brought up onto the Protium X3 system for accelerated software validation. It is a Yin and Yang arrangement, or as Cadence calls it, a Dynamic Duo.
“With the new 4-State Emulation App, we can accelerate the low-power verification of our complex SoC designs, improving our verification accuracy and low-power coverage while improving overall verification throughput.” Seonil Brian Choi Vice President, Samsung Electronics"As SoCs become more complex, scalable validation and verification tools that enable massive software testing before tapeout are more critical than ever," said Tran Nguyen, senior director of design services, Arm.
EDA Prototyping EDA Emulation AMD FPGA In EDA
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