UC Irvine researchers combine analog and digital signal processing to create transmitter and receivers that can deploy 6G.
Researchers at the University of California, Irvine, have developed a 140-gigahertz wireless chip that can power the transition to 6G and more advanced transmission protocols at speeds that match fiber-optic cables.
To do so, the researchers combined digital and analog signal processing, according to a university press release. Development of this chip has been underway since 2020. The team of researchers led by Payam Heydari, a professor of electrical engineering and computer science at UC Irvine, had long recognized that conventional chips would soon hit a performance wall. “We realized that to reach the elusive 100-gigabit-per-second milestone – which is 100 times the speed of current wireless devices – without melting the chip, we had to fundamentally rethink the circuit topology,” said Heydari in a press release. Building a new transceiverResearchers working with wireless devices are well aware that as wireless speeds increase, the energy required to process the data increases exponentially. If the same architecture is used for future transceivers, the battery life would need to be higher by the same amount, or the device would discharge immediately. Modern-day transmitters create signals using digital-to-analog converters. For 6G and beyond, these transmitters would have to operate at frequencies above 100 GHz, which are both incredibly complex and power hungry. Researchers call this the DAC bottleneck. Heydari’s team eliminated the DAC bottleneck by constructing signals directly in the radio-frequency domain using three synchronized subtransmitters. Called the RF-domain 64QAM, this allows the chip to be extremely efficient since it can send more data without overheating. Hierarchical Analog DemodulationHowever, this only solves a part of the problem. Receivers also used analog-to-digital converters to convert the received data into digital form. At extreme speeds, one reaches the sampling bottleneck, which can consume significant power, making it infeasible for use in devices such as smartphones. So, the team built a smarter receiver, too. Components of the receiver chip of the wireless transceiver system developed by UC Irvine electrical engineers include the RXFE, receiver front-end; VGA, variable gain amplifier; CTLE, continuous-time linear equalizer; CDR, clock and data recovery; and BB, base band. Payam Heydari / UC Irvine. “We developed a technique called hierarchical analog demodulation,” explained Youseef Hassam, formerly a postdoctoral researcher at UC Irvine and now working at Qualcomm. “By breaking the signal down hierarchically in the analog domain, peeling apart the complex data layers before they’re digitized, we extract the data using a fraction of the power typically required.”The new receiver chip, designed by the team, uses a 22-nm architecture but consumes only 230 milliwatts of power. In addition to enabling transmissions in the 140 GHz range, the chip’s architecture enables mass production, thereby enabling large-scale adoption. “We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables,” said Heydari. “By operating in the F-band – a frequency range well above current 5G standards – we can offer massive bandwidths that will transform how machines, robots, and data centers communicate.”“Our innovation eliminates the need for miles of complex copper wiring inside data centers,” he added. “Data farm operators can do ultrafast wireless links between server racks, saving considerable money on hardware, cooling, and power.”The research findings were published in separate papers about the transmitter and receiver in the IEEE Journal of Solid-State Circuits.
Computer Science DAC Bottleneck Fiber Optic Cables Hierarchical Analog Demodulation Inventions And Machines RF-Domain 64QAM Sampling Bottleneck UC Irvine Wireless Chip
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